Responsibilities:
- Responsible for block performance and IP Verification
- In charge of executing verification plans based on specifications
- Create test benches using UVM-based constrained-random and formal methods
- Conduct SoC Integration and Verification, which includes, testing and debugging use cases for low-power design and SoC
- Ensure the smooth process of methodologies to streamline IP development and integration
Requirements:
- Minimum 5 years of IC design experience
- Possess knowledge required in developing test benches and verification components using SystemVerilog and UVM
- Experienced in scripting/language (Python, PERL, Shell, TCL), and Design/Verification skills
